1. Field of the Invention
The present invention relates to a digital phase delay locked loop (DLL), and in particular, to an improved phase delay correction apparatus which is capable of embodying a precise resolution and an indefinite delay range with a minimum number of delay units by applying a domain classifying concept.
2. Description of the Conventional Art
As shown in FIG. 1, a conventional phase delay correction apparatus includes a phase detector 101 for outputting a comparing signal (RL) by comparing the phase of a chip clock signal (CCLK) on the basis of a system clock signal (SCLK), a phase adjusting unit 102 for outputting a phase-adjusted clock signal (YCLK) by sequentially delaying the system clock signal (SCLK) in accordance with the comparing signal (RL) of the phase detector 101, and a clock signal distributor 103 for supplying the phase-adjusted clock signal (YCLK) to the inside of a chip by distributing the phase-adjusted clock signal (YCLK) of the phase adjusting unit 102 and for feeding back the phase-adjusted clock signal (YCLK) to the phase detector 101 as the chip clock signal (CCLK).
As shown in FIG. 2, the phase adjusting unit 102 includes a shift register 41 for shifting the data "1" by one bit to the right from the input side (DR) when the comparing signal (RL) of the phase detector 101 is "1", synchronized with the clock signal (CLK) and for shifting the data "0" by one bit to the left from the input side (DL) when the comparing signal (RL) thereof is "0", synchronized with the system clock signal (SCLK) , and a plurality of delay units 42-1, 42-2, . . . 42-n for outputting a phase-adjusted clock signal (YCLK) by sequentially delaying the system clock signal (SCLK) in accordance with each bit value (B1 . . . Bn) of the shift register 41.
The plurality of delay units 42-1,42-2 . . . 42-n include first inverters 1 each for inverting a system clock signal, first pass gates 2 connected in parallel with the output terminals of the first inverters 1 and which are turned on when the corresponding bit value of the shift register 41 is "1", second pass gates 3 the output terminals of which are commonly connected to the output terminals of the first pass gates 2 and which are turned on when the corresponding bit value of the shift register 41 is "1", and second inverters 4 for outputting the phase-adjusted clock signal (YCLK) by inverting the outputs of the first inverters 1 inputted through the first pass gate 2 or the clock signal which is fed back from the succeeding delay unit through the second pass gate 3.
In the last delay unit 42-n, two inverters 5,6 are additionally connected in series between the first inverters 1 and the second pass gate 3.
Referring to FIG. 1 and FIG. 2, the operation of the conventional phase delay correction apparatus will now be described in detail.
The phase detector 101 compares the phase of the system clock signal (SCLK) with the phase of the chip clock signal (CCLK) and outputs the comparing signal (RL) to the phase adjusting unit 102, wherein the comparing signal (RL) is "1" when the phase of the chip clock signal (CCLK) is leading, and is "0" when the phase of the chip clock signal (CCLK) is trailing.
Here, as shown in FIG. 2, when the comparing signal is "1", the shift register 41 of the digital data line 102 shifts the data "1" by one bit from the input side (DR) to the right side, synchronized with the system clock signal (SCLK), and when the comparing signal is "0", synchronized with the system clock signal (SCLK) , the shift register 41 shifts the data "0" by one bit from the input side (DL) to the left, and outputs the bit values to the plurality of delay unit 42-1,42-2, . . . ,42-n.
Therefore, as the first and second pass gates 2,3 of the plurality of delay units 42-1,42-2, . . . ,42-n are turned on complementarily in accordance with each bit value (B1,B2, . . . ,Bn) shifted to the right or the left, a delay chain is formed comprising the first inverters 1 and the second inverters 4.
For example, when all the bits of the shift register 41 are "0", the first pass gates 2 are all turned on, and the second pass gates 3 are all turned off, and therefore, only the inverters 1,4 of the delay unit 42-1 form a delay chain, and the minimum delay of the system clock signal (SCLK) occurs.
Through the delay units 42-1,42-2, . . . ,42-n, the phase- adjusted clock signal (YCLK) is outputted to the clock signal distributor 103, which outputs a chip clock signal (CCLK) to the inside of the chip for detecting various versions of clock signals and phases within the chip, and feeds back the same and the phase detector 101. Afterwards, the identical operation is repeated.
However, since the delay range according to the conventional phase delay correction apparatus depends on the number of the delay units, the number of the delay units should be arranged so that a minimum delay occurs and a phase shift of more than 360.degree. may be achieved.
But, in the delay unit of the phase adjusting unit, a delay occurs through two inverters and one pass gate in a minimum delay condition, and when the delay is increased, since the delay through one pass gate is added, it has been difficult to achieve a resolution below 400 ps(Pico sec) due to the increase in the delay.